Security & Encryption IP-cores by intoPIX

The family of IPX-AES IP-Cores provides an efficient FPGA implementation of the Advanced Encryption Standard (AES). Its flexibility allows the combination of several functions and operating modes for a very small FPGA footprint.

The family of IPX-AES IP-Cores is an encryptor / decryptor core range that efficiently implements the Advanced Encryption Standard as specified in the Federal Information Processing publication FIPS-197 of the National Institute of Standards and Technology in FPGAs.

The IPX-AES module can be customized to ensure its optimization for a wide range of specific application fields with a design architecture that can be adapted to support low up to very high bit-rates. On top of its Multi-Gigabit capability, its flexibility allows combining several functions and operating modes on very small footprints.

Functions

With addressing keys of 128 (or 256), the IPX-AES cores execute decryption or encryption.

Data-stream handling
The IPX-AES cores can handle the data and secret keys in two different ways. The single stream option consists of a core capable of managing data with a single key, before a new update of this key. The multiple stream option is a feature capable of managing multiple ciphering processes together, each based on a different secret key.

Chaining modes
The inter-data-block chaining supports all existing modes that can be used separately or combined into a single design: ECB (Electronic Code-Book), CBC (Cipher Block Chaining), CTR (Counter). Other modes could be supported.

Data bus
The incoming, outgoing and key data are handled on either common or separate buses. Data bus width is 128 bits.

Clock
The processes use a single clock and can be reset asynchronously.

* or higher

IP-cores resources available on request

The modular exponentiation accelerator IPX-RSA is an efficient arithmetic coprocessor for the RSA public-key cryptosystem. It performs the Ae mod M calculation and therefore offloads the most computer-intensive operation of RSA from the main processor. The RSA cryptosystem can be used for public key encryption, decryption and signature/authentication. It is currently the most deployed public key scheme and is used in well-known standards such as SSL/TLS secure internet access, IPSec Virtual Private Networks and S/MIME secure email.

The key advantage of the IPX-RSA IP-Core is its low footprint, thanks to an efficient balance between logic fabric and embedded RAMs and Multipliers.

Taking advantage of its high operating frequency, it is capable of achieving a high throughput of modular exponentiations. As a result, this IP-Core provides a good compromise between processing time and resources compared to general purpose processors.

Other features of the IPX-RSA core are self-support and ease of use. The IP-Core needs no interaction with the main processor during computation and requires no pre/post computation of the base and exponent (A and e). It is also accessed through a simple 32-bit processor bus.

IP-cores resources are available on request

IPX-HMAC-SHA-1 IP-Core is the hashing function required for the content integrity check and content identification as specified in DCI document v1.2. It is designed for Xilinx and Intel FPGA devices.
IPX-HMAC-SHA-1 is an implementation of the Key Hashed Message Authentication Code standard, which describes a mechanism for message authentication using cryptographic hash functions. It enables computation of the keyed hash message authentication code (HMAC) for audio and video assets.

This HMAC module uses the SHA1 core in combination with a secret key and the text message provided by the user in order to generate a fixed length MAC value.
The key advantages of the IPX-HMAC-SHA-1 IP-Core are its high throughput and low latency. Its interface can handle a frequency of at least 125 MHz, which is highly suitable for applications like Gigabit Ethernet.

IP-cores resources are available on request

Specialized in cryptography and forensic marking, intoPIX JPEG 2000 Cinema Decoder IP-cores have been designed with a dedicated interface for Forensic Marking. 

The interface facilitates the integration of watermarking functions within the decoding process.

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