IP -核心 FPGA & ASIC

Overview
特征
配置
联系我们
Related info

TicoRAW is the new RAW !

intoPIX TicoRAW is a revolutionary RAW (Bayer) image processing and compression technology, extremely tiny and low power.


intoPIX has developped various architectures running at different pixel per clock to target a wide range of pixel rates/ frame rates/ image sensors resolutions and a wide range of FPGA devices & ASIC technology nodes. Encoding or Decoding can be achieved into the small AMD-Xilinx & Intel FPGAs, robust for real-time operation with no latency. intoPIX offers silicon-proven IP with very low gate count & SRAM consumption in ASICs.


随着可用图像、图像传感器和视频分辨率的快速发展,对处理RAW/图像传感器数据的新方法的需求比以往任何时候都大。 


With TicoRAW, you can capture, transmit, store, edit, preserve, analyze,.. RAW Bayer data "more efficiently" with small bandwidth and file sizes, preserving the full flexibility of "RAW".


IP核的特点

TicoRAW IP-cores are fully available and silicon-proven for FPGA and ASIC designs

 Image / Video 
  •  色彩空间。(CFA-BAYER) - RGGB、RCCB等。
    • optional  Monochrome/Greyscale and 4:2:2* modes
  • BIT DEPTH : 8, 10, 12, 14, 16
  • Resolutions: Any (2Mpx to 160Mpx or more (see example for, HD, 2K, 4K, 8K, 10K hereunder) 
  • 像素率/帧率*:任意(取决于-核配置和目标设备)。
TicoRAW Processing &  Compression
(Latency, Quality, Rate Control)  
  • (子)帧内:降至0.1毫秒以内
  • 实时操作保证(无溢流或下溢) 
  • 固定延迟 - 只有几行像素(行数取决于配置文件)
  • 可调节的压缩率低至每像素1位的压缩率
  • Support for lossy / visually lossless / near-lossless / mathematically. lossless 
  • CBR (Constant Bit Rate) operation (optional : Constant Quality mode)
  • ISP proxy output within decoder (Decoder IP-core Addon)
FPGA / ASIC 实现
  • Various Pixel Per Clock architectures available to achieve the minimal footprint into the chip.
  •  在任何FPGA中实现低成本:非常低 FPGA 逻辑和内部 RAM 使用(无需外部 DDR)
    • Fit in Xilinx (AMD) Spartan-6, Artix-7, Kintex-7, Kintex Ultrascale, Zynq, Virtex Ultrascale, UltrascalePlus, Versal
    • Fit in Intel Cyclone V,  Arria V, Stratix V, Cyclone 10, Arria 10, Stratix 10, Agilex
    • Fit in Lattice 
  • Low Gate Area (low gate count / low memory) for ASIC - Silicon Proven
  • 编码器和解码器的复杂性大致相同 
  • IP-core customizable per application 

* in 422 , the frame rate will be the half of the frame rate achieved in RAW Bayer mode

NEW - HD, 4K, 8K, 10K, 16K, 20K RAW ...
and your configuration for FPGA & ASIC

基于我们支持的所有功能,可以提供自定义版本,以满足您的特定需求。 

联系我们了解您自己的配置。 


See hereunder a list of typical configurations. The Max fps will depend on the selected encoder /decoder and its related pixel-per clock architecture.


IP-CORES
-ENC  / -DEC
 颜色采样
Sensor
Bit depth
Resolutions examples
Max fps
在100MHz时*
Max fps
在250MHz时*
Max fps
 at 300 MHz*
Max fps
在1GHz时*
 IPX-TicoRAW-2K
(up to 2048-pixels width)
 RAW CFA Bayer  8, 10, 12, 14, 16
 2048 x 1080
2048 x 2048
 670
354
  839
442
 1006
530
  3354
1769
 IPX-TicoRAW-4K
(up to 4096-pixels width)
RAW CFA Bayer 8, 10, 12, 14, 16
 4096 x 2160
4096 x 4096
 168
88
 209
110
 250
132
 837
441
 IPX-TicoRAW-8K
(up to 8192-pixels width)
RAW CFA Bayer
 8, 10, 12, 14, 16
8192 x 4320
8192 x 8192
44
22
105
55
124
68
418
220
...
ASK FOR YOUR CONFIGURATION 

 * Max Frequency (MHz) of the IP-cores can be adjusted according to your selected pixel-per-clock architecture, and your targeted FPGA or ASIC technology node

Contact us for more information about our TicoRAW

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资源 

TicoRAW Solutions overview
Download the product sheet

相关解决方案

TicoRAW Libraries for CPU & GPU

Related News

Read our TicoRAW blog articles